I finally found the ICE40 FPGA HDMI timing bug, and much more progress!

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[stream] iCE40 / FPGA IO timing analysis explanation and examples [stream] iCE40 / FPGA IO timing analysis explanation and examples
My first Hello World on the ice40hx-8k Breakout Board My first Hello World on the ice40hx-8k Breakout Board
[002] Testing the Linux Kernel driver for the Lattice iCE40 FPGA [002] Testing the Linux Kernel driver for the Lattice iCE40 FPGA
How to fix Timing Errors in your FPGA design during Place and Route, meeting clock constraints How to fix Timing Errors in your FPGA design during Place and Route, meeting clock constraints
FPGA DEV: A brief look at the iCE40 Phase Locked Loop: Multiplying a 3.58 MHz clock up to 42.96 MHz! FPGA DEV: A brief look at the iCE40 Phase Locked Loop: Multiplying a 3.58 MHz clock up to 42.96 MHz!
Got FPGA Timing Problems? Got FPGA Timing Problems?
Getting started with the Lattice iCE40 FPGA: Architecture and Technical Details (Part 2) Getting started with the Lattice iCE40 FPGA: Architecture and Technical Details (Part 2)
NVIDIA Just Changed PHYSICS Forever NVIDIA Just Changed PHYSICS Forever