Basic Gate from myHDL to Vivado to PYNQ-Z1

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AND Gate myHDL PYNQZ1 AND Gate myHDL PYNQZ1
Seeded Ring Counter RTL IP Hookup in Vivado from myHDL to PYNQ-Z1 Seeded Ring Counter RTL IP Hookup in Vivado from myHDL to PYNQ-Z1
NOT Gate myHDL PYNQZ1 NOT Gate myHDL PYNQZ1
XORGate myHDL PYNQZ1 XORGate myHDL PYNQZ1
myHDL 4:1 MUX written in gate level logic on PYNQ-Z1 (non SoC) myHDL 4:1 MUX written in gate level logic on PYNQ-Z1 (non SoC)
myHDL 2:1 MUX written in gate level logic on PYNQ-Z1 (non SoC) myHDL 2:1 MUX written in gate level logic on PYNQ-Z1 (non SoC)
myHDL 1:4 DEMUX via behavioral using bit vectors on the PYNQ-Z1 (non SoC) myHDL 1:4 DEMUX via behavioral using bit vectors on the PYNQ-Z1 (non SoC)
myHDL 1:4 DEMUX written in gate level logic on the PYNQ-Z1 (non SoC) myHDL 1:4 DEMUX written in gate level logic on the PYNQ-Z1 (non SoC)