Brett Cline, Codasip - RISC-V customization, HW/SW co-optimization, and custom compute

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Codasip’s approach to custom compute Codasip’s approach to custom compute
Architecting ambitions with custom compute #ew23 #embeddedworld Architecting ambitions with custom compute #ew23 #embeddedworld
Welcome to Codasip Welcome to Codasip
Customizing RISC-V cores to accelerate neural networks | Jon Taylor at EW22 Customizing RISC-V cores to accelerate neural networks | Jon Taylor at EW22
Finetuning RISC-V hardware to your software using Custom Bounded Instructions Finetuning RISC-V hardware to your software using Custom Bounded Instructions
Codasip at Embedded World 2023 - Day 1 Codasip at Embedded World 2023 - Day 1
RISC-V customization demo: AI-based image denoising RISC-V customization demo: AI-based image denoising
Codasip stand at Embedded World 2022 - RISC-V pavilion Codasip stand at Embedded World 2022 - RISC-V pavilion